Portable electronic devices present significant design challenges because they require displays that are small in size, relatively high in resolution and low in power dissipation. The electronics that drive small format displays must also occupy a small footprint and minimize the external component count. The ideal display driver needs to be flexible because a large number of different types of liquid crystal display (LCD) materials exist with different drive requirements.
A relatively high resolution data converter is necessary to drive the liquid crystals with adequate resolution due to the fact that displays are highly non-linear. An ideal display driver architecture should be easily expandable in the number of outputs and resolution to accommodate larger displays with higher resolution.
There are many portable electronic devices that require low power, small area digital-to-analog converters (DACs). Such devices include, without limitation, small format display drivers for personal digital assistants (PDAs), image viewers, headset displays, cell phones, game players, remote control devices, remote data acquisition and control modules, portable instruments, portable sound systems, and other types of devices that require a voltage output that is proportional to a digital value.
DACs are general purpose building blocks for providing an analog voltage or current that is proportional to a digital value that is presented to its inputs. DACs are commonly used to provide an analog output signal from a digital processing system such as a computer. One can view a DAC as a black box that converts a digital word into a corresponding analog signal that represents the same approximate percentage of full scale.
Small format electronic displays are commonly used in portable electronic instruments. Liquid crystal display (LCD) technology is a popular display technology because of its good display properties and low power dissipation. A display array comprises a plurality of small display dots called pixels that are arranged in a row and column structure. The information to be displayed on a single pixel requires selection of the pixel location and the corresponding value for the intensity of light to be transmitted by the pixel. The intensity of light to be emitted can vary over a range of five hundred twelve (512) to one (1) or larger depending on the video or image program information requirements.
In the case of pixel displays, DACs are used to translate a digital value into an analog signal that corresponds to the proper light intensity for a pixel.
Because extreme price pressures exist on the manufacture of display modules, the design of display modules is limited to basic complementary metal oxide semiconductor (CMOS) technology. A basic CMOS process does not contain low threshold voltage transistors, high sheet resistance poly resistors, or poly to poly capacitors. Integrated circuits for display drivers must be designed around these limitations.
Therefore, the technology available for designing small format LCD display drivers imposes stringent requirements on the design of column driver digital-to-analog converters (DAC). The column driver DACs must be small in size, exhibit fast settling time, and dissipate low quiescent power. The DAC architecture must also be easily expandable with multiple channels to support higher display resolutions.
A quarter VGA (Video Graphics Array) display comprises an array of three hundred twenty (320) pixels by two hundred forty (240) pixels. A quarter VGA display using an eighty (80) to one (1) source line multiplex ratio on the display panel requires twelve (12) DAC channels to drive the nine hundred sixty (960) source lines on the display panel. A display panel with a sixty Hertz (60 Hz) frame rate, two hundred forty (240) lines, and no blanking, requires a maximum pixel refresh time of eight hundred sixty (860) nanoseconds.
A common prior art approach to driving small format displays is to use a plurality of resistors in a reference resistor string as a voltage reference for the DAC. A digital word decoder selects the resistor voltage tap on the reference resistor string that corresponds to the desired analog voltage and passes it to an output amplifier. This type of DAC architecture is referred to as an R-string DAC architecture. R-string DACs are popular because the output is monotonic and one can develop a DAC conversion compensation curve by using non-equal resistor segments in the reference resistor string. A DAC conversion compensation curve permits correction for the non-linear transmissivity of LCD display material and the response of the human eye.
FIG. 1 illustrates a schematic representation of a conventional R-string DAC architecture 100 that comprises a number (M) Of DAC channels. DAC architecture 100 comprises a reference resistor 110 associated with the first DAC channel (i.e., DAC Channel 1). One end of reference resistor 110 is coupled to power supply VDD and the other end of reference resistor 110 is coupled to ground. Reference resistor 110 comprises a number (2N−1) of resistor segments (designated R1 through R2N−1) coupled together sequentially.
DAC architecture 100 also comprises a number (M) of multiplexers that are designated with reference numerals 120(1) through 120(M). There is one multiplexer 120 for each of the M DAC channels of the DAC architecture 100. The multiplexer 120(1) that is associated with DAC Channel 1 is designated as MUX Channel 1. The multiplexer 120(M) that is associated with DAC Channel M is designated as MUX Channel M. The inputs of each multiplexer are coupled to the reference resistor 110 between each of the 2N−1 resistor segments.
The reference voltages from the reference resistor 110 are digitally selected by the multiplexers 120. As shown in FIG. 1, the inputs of MUX Channel 1 are connected to the reference resistor 110 between each of the 2N−1 resistor segments. MUX Channel 1 digitally selects the reference voltages from the reference resistor 110. The other multiplexers operate in the same manner.
The reference voltage that is selected by each of the M multiplexers 120 is output to an associated output buffer. There is one output buffer associated with each multiplexer. The M output buffers are designated with reference numerals 130(1) through 130(M). The output buffer 130(1) that is coupled to MUX Channel 1 is designated as Output Buffer 1. The output buffer 130(M) that is coupled to MUX Channel M is designated as Output Buffer M.
The internal load capacitance (designated CINT) between a multiplexer and its output buffer comprises the parasitic capacitances of routing, multiplexer devices, and the input capacitance of the output buffer. The selected reference voltage is passed through its respective output buffer to drive a large panel capacitance (designated CPANEL).
The use of R-string DAC architecture is hampered by the presence of increased power dissipation in the R-string and poor settling time. Some prior art R-string DAC architectures use resistor segments in the R-string that have non equal values of resistance. Some other prior art R-string DAC architectures use a higher resolution R-string DAC that employs a look up table for curvature correction. Both of these prior art approaches require excessive power consumption.
The prior art DAC architecture 100 shown in FIG. 1 exhibits significant deficiencies. One deficiency is that there is a major time constraint in the reference resistor string and in the parasitic capacitances that must be driven. Another deficiency is that there is another major time constraint in the multiplexer parasitic resistances and capacitances.
Therefore, there is a need in the art for an improved ultra low power scalable DAC architecture that is optimized for small format liquid crystal display (LCD) applications. Specifically, there is a need in the art for an improved ultra low power scalable DAC architecture that can remedy the above described deficiencies of prior art DAC architectures.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.